Clockgen Pll Control Download

ClockGen might not be as popular, but allows you to overclock a lot of different system devices: CPU, memory, AGP and PCI bus! However, this greatly depends on your system specs. On my system ClockGen did not find the clock generator that is needed for “PLL Control” and “PLL Setup”, so it's pretty. Apr 25, 2009 Overclocking using Clockgen, revised edition. Though clockgen may not have your exact PLL. Go to Control PLL and slowly move the FSB.

SetPLL is a wrapper over r-w everything to program a PLL. Advantages over setfsb being: 1. It's free - no Paypal US$10 donation cost to try an overclock.

It's much faster than setfsb in setting your FSB. Unlike setfsb, to set the BCLK it's only writing to the PLL.

A PLL read isn't needed so there are no side-effects like sata controllers hanging or problems with sleep followed by resume. The PLL data to be written is fully configurable to your specific requirements. Has an optional resume-from standby/hibernate script to automate your overclock. What operating systems are supported? Tested: Win7/64 and WinXP x86.

Untested: other Win7/Vista/XP. What PLL definition files are supplied with setPLL?

A command-like window will popup in the background. Can get rid of the popup window with one of two ways. Disable User Access Control (UAC) in Control Panel or ii.

Edit setpllsetpll.bat and change the two entries that containing rww /min /command=setPLL.rw%OUT% to rww /min /command=setPLL.rw 2. HDX9000: needs a 'setPLL -read 0x0D' command run before doing the first BCLK set with 'setPLL ics9lprs501pglf [BCLK]' or else it freezes. Dual-IDA mode sees chkcpu32-based 'cpu' reporting the frequency and off by one multipler. This is just a reporting bug.

The BCLK is still calculated correctly. If don't have battery in the system when resume-setPLL.vbs starts up then will have a startup error 'line 26, char 1: Invalid procedure call or argument', since it requires the PowerManagement module to do AC/DC profile switching. Install the battery to correct this error. 'setPLL -read' will occasionally provide incorrect data with many bytes being 0xFF. Re-run again to get proper data. What additional utilities are included in setPLL package? Utility Purpose Usage automated Folder of scripts to automatically set your AC or DC clocks on startup, during ACDC switch & after a resume-from-standby/ hibernate.

Shortcut resume-setPLL.vbs in startup folder to use. '************************************************************************ 'User-edittable section '************************************************************************ ' start_delay: the delay time in msec to delay prior to running AD/DC script ' AC/DC_script: the script OR command to run on initial run, during AC DC ' switch and on resume-from-standby/hibernate. Const start_delay=2000 Const AC_script='c:setPLLautomatedAC-overclocked' Const DC_script='c:setPLLautomatedDC-normal' setIGP to alter the Core Render Clock on GM950/X3100/4500MHD IGPs. A downclock + Maximum Battery in Intel IGP systray giving greatest glitch-free stable setPLL overclock. C:setPLL>hpfan HP Elitebook SMSC-controller based fan control HPfan ac [-save]: apply AC profile HPfan dc [-save]: apply DC profile HPfan hp [-save]: apply HP profile - set back to HP defaults -save: save current fan params to the specified profile. Do the AC & DC profile after setting fan with hwinfo32.

HPfan -clear: delete existing AC, DC and HP profiles DSDT iasl+asl utils to create a custom DSDT override for fan control. N/A devset (devcon) ~Device Manager for use in your batch files/scripts. Acknowledgments Thank you to maddi2k, Moral Hazard, DavyGT and 2.0 for testing and supply confirmed working [PLL].lut example files; Jeff, the author of r-w everything, for providing his most excellent SMBUS read/write ability with his package plus enhancements. Revision history.

1.0f (4-4-11) -------------- NEW: Additional OC related utilities included. Automated -Folder of scripts to do automated overclock.

SetIGP - to increase/decrease Core Render Clock on GM950/X3100 GMAboost - a GMABooster clone to do a netbook GMA950 overclock HPfan - to save/load HP Elitebook fan profiles DSDT - iasl+asl to create a custom DSDT override for fan control devset - (devcon) to optionally enable/disable devices NEW: setPLL -report now sets 'cpu' and 'cpu_bclk' DOS variable for your own batch file queries. Also does this after setting a BCLK. NEW: '-read' now dumps [READBACK_BYTE (0xC)] bytes as is set on PLL NEW: '-read [READBACK_bytes]' sets that PLL register then does '-read' NEW: Added half-multiplier support to chkcpu32-based cpu.bat NEW: start_delay parameter in resume-setPLL.vbs NEW: no longer have brief r-w minimized startup flash screen. FIX: PLL smbus read/write command endbyte was off by one byte FIX: pcie line fixed in myPLL.lut template creation. FIX: more accurate cpu_bclk frequency reporting FIX: removed last delay after setting the final BCLK in a list UPDATE: Added 127,129,131,133 pci-e clocks to ics9lprs387/397 UPDATE: ics9lprs501pglf.lut revised and tested on HDX9000.

UDPATE: revised commandline usage output. UPDATE: cpuz 1.56 ->cpu-z 1.57. UPDATE: r-w everything 1.4.9.1->1.4.9.10.

New /command /stdout parms. 1.0e (3-14-11) -------------- BUG FIX: to be able to run setPLL by giving it's full path, eg: c:setPLLsetPLL ics.

So resume-setPLL.vbs will now work. BUG FIX: delay was off by 1 second. BUG FIX: ics9lprs387bklf to allow pci-e clock changes. Added -read param to read PLL data and initialise myPLL.lut Set default delay parameter when specifying a list of BCLKs to 1 second. Added comments explaining PLL config registers to ics9lprs387/397.LUT Fixed some typos and revised in setPLL.txt Included DavyGT's latest m11xR2.lut up to 197Mhz BCLK 1.0d (3-1-11) -------------- Commandline syntax changed. If using -preview it must be first Added PCIE clock options to commandline Using new r-w BSWAP command (swap little/big endian) so can now create LUT.bat files by transcribing setfsb format directly Changed existing LUT files to setfsb format Added PCIE clocks to ics9lprs387/397 LUT files Updated r-w everythng to 1.4.9.1 1.0c (2-19-11) -------------- Changed cpu.bat to use CrystalCPUID as the default mechanism to report the BCLK.

Chkcpu32-based cpu.bat supplied in extras directory Improved speed by not reporting current FSB when doing a PLL write Cut down rw-everything to be only required files Added partial HDX9000 ics9lprs501pglf PLL Added RST BCLK entry to ics9lprs387/397 and ics9lprs355 1.0b (2-17-11) -------------- Replaced chkcpu32 with CrystalCPUID for better BCLK reporting Changed all references from FSB to the more accurate BCLK Skip comparison to current BCLK. Always write PLL unless do -preview Updated to r-w everything 1.4.9 Include m11xR2 PLL 1.0a (2-13-11) -------------- Released with r-w everything that runs minimized 1.00 (2-12-11) --------------- Initial release. The fan control looks interesting and I'll try it out. Unless 2 cores are in C6 the system will reduce my multiplier by 1 at 70C, and again at 80C. The BIOS doesn't set the fan to full blast until 85C, so fan control would be nice. With speedfan I can set the fan, but in less than half a second the BIOS overrides my setting, slowing the fan back down again. If I hit the keys really fast I can kinda overpower the BIOS, but that isn't very practical.

The fan control in setPLL works with HP 2530P and probably other Montevina (last C2D) and Calpella (1st gen i-core) HP Elitebook units. No Dell unfortunately. However, try the the FN+15324 trick explained. I can see too that i8kfangui doesn't work based on your comments at so speedfan looks to be it. The fan control looks interesting and I'll try it out. Unless 2 cores are in C6 the system will reduce my multiplier by 1 at 70C, and again at 80C.

The BIOS doesn't set the fan to full blast until 85C, so fan control would be nice. With speedfan I can set the fan, but in less than half a second the BIOS overrides my setting, slowing the fan back down again. If I hit the keys really fast I can kinda overpower the BIOS, but that isn't very practical. Try HWiNFO to control your fans, if it doesn't work out of the box, contact (the author), in many cases he can enable fan control quite easily, depends on the machine really.

Wow, I just discovered this program, which seems a great alternative to setFSB! I'm trying to overclock a Vaio vgn-fe21 with a T7200 cpu. I was using setFSB and it was very easy to increase the fsb clock, but I was a little concerned because overclocking the fsb was also increasing the ram frequency, PCI and PCI-E bus frequencies.

Does this also apply to OC by using setPLL instead of setFSB? I've googled for the subject but I haven't been able to find out what the consequences would be with an overclocked ram, PCI and PCI-E. In particular I'm concerned about PCI and PCI-E, because I have no idea if this could fry the connected peripherals (the gpu?) or maybe the motherboard too. How far should I go with this to avoid risking my hardware?

Wow, I just discovered this program, which seems a great alternative to setFSB! I'm trying to overclock a Vaio vgn-fe21 with a T7200 cpu.

I was using setFSB and it was very easy to increase the fsb clock, but I was a little concerned because overclocking the fsb was also increasing the ram frequency, PCI and PCI-E bus frequencies. Does this also apply to OC by using setPLL instead of setFSB? I've googled for the subject but I haven't been able to find out what the consequences would be with an overclocked ram, PCI and PCI-E. In particular I'm concerned about PCI and PCI-E, because I have no idea if this could fry the connected peripherals (the gpu?) or maybe the motherboard too. How far should I go with this to avoid risking my hardware? SetPLL was written originally because I wanted to overclock a 2530P's FSB to run faster CPU+MEM and more importantly, overclock the pci-e bus for faster eGPU performance.

It uses look up table files (.LUT) to program your PLL, an idea that I got from perusing a setFSB clone for Linux. I also wanted it to be *free* so other 2530P users could do the same.

It was important too that users could add their own PLL to be supported. Anybody who has a programmable (not TME-locked) PLL, has the PLL datasheet and can decipher it would be able to add support for their machine. SetPLL is also considerably faster at programming the PLL than setFSB is.

To answer your question, it will depend on how programmable you PLL is to answer whether the FSB and pci-e clocks can be programmed separately. The example LUT files included with setPLL have both the FSB and PCI-E clocks for several PLLs where both can have both programmed. I found that pci-e overclocks over 12% usually result in the wifi card failing.

Is it possible to add additional BCLKs to setPLL for a supplied definition PLL? The provided definition.lut file for ics9LPRS387bklf BCLKs start at 266 and go through 357. Unfortunately that’s too high for my use.

I need it to start at BLCK of 200. How can I add BCLK 200 to 265?

Edit: never mind, I now understand after looking further into the lut file. Background: I have an Acer eMachines E725-4520, PLL, GL40 chipset & T4400 x11 800MHz FSB CPU. I just recently completed a PLL hardware mod to enable TME (pin #14 to gnd via 10K resistor). I used the freeware setFSB with the PLL diagnosis clock generator (9LPRS387 is not supported) to manually set the registers as shown by Dufus here: I was able to increase BCLK from 200 to 217MHz, going any higher I get a white screen.

Trying for a higher OC, I then increased the CPU voltage via a CPU pin mod of +.1V, which I confirmed by the moderate increased heat. But again a white screen at 217Mhz with no improvement in BCLK. Memory is not the issue either as mem peaks at 433Mhz with this small OC and current SPD memory timings of 6-6-6-18 at the lowest JEDEC of 457MHz 6-6-6-18, so plenty of room. In an attempt to achieve a higher OC and bypass setFSB incase I was doing something wrong there, I attempted an FSLx PLL pin mod from 200 to 266 by disconnecting the CPU and MCH from the PLL on pin #2 (FSLB) and then connecting pin #2 to gnd.

GL40 only supports 667/800FSB. But I was in hopes this would allow me to trick the CPU and Chipset to 266Mhz. However, it would not POST, so I backed it out. I’m not sure what the limiting factor is in both instances, maybe it’s the GL40 chipset.?

Any help would be appreciated as I’m trying to stretch the life of this laptop. Is it possible to add additional BCLKs to setPLL for a supplied definition PLL?

The provided definition.lut file for ics9LPRS387bklf BCLKs start at 266 and go through 357. Unfortunately that’s too high for my use. I need it to start at BLCK of 200. How can I add BCLK 200 to 265? Edit: never mind, I now understand after looking further into the lut file. Background: I have an Acer eMachines E725-4520, PLL, GL40 chipset & T4400 x11 800MHz FSB CPU.

I just recently completed a PLL hardware mod to enable TME (pin #14 to gnd via 10K resistor). I used the freeware setFSB with the PLL diagnosis clock generator (9LPRS387 is not supported) to manually set the registers as shown by Dufus here: I was able to increase BCLK from 200 to 217MHz, going any higher I get a white screen. Trying for a higher OC, I then increased the CPU voltage via a CPU pin mod of +.1V, which I confirmed by the moderate increased heat. But again a white screen at 217Mhz with no improvement in BCLK. Memory is not the issue either as mem peaks at 433Mhz with this small OC and current SPD memory timings of 6-6-6-18 at the lowest JEDEC of 457MHz 6-6-6-18, so plenty of room. [ATTACH=CONFIG]6032[/ATTACH] In an attempt to achieve a higher OC and bypass setFSB incase I was doing something wrong there, I attempted an FSLx PLL pin mod from 200 to 266 by disconnecting the CPU and MCH from the PLL on pin #2 (FSLB) and then connecting pin #2 to gnd. GL40 only supports 667/800FSB.

But I was in hopes this would allow me to trick the CPU and Chipset to 266Mhz. However, it would not POST, so I backed it out. Zard Single Collection 20th Anniversary Rarity on this page. I’m not sure what the limiting factor is in both instances, maybe it’s the GL40 chipset.?

Any help would be appreciated as I’m trying to stretch the life of this laptop. Try decreasing your 4500MHD iGPU clocks by setting the Intel GFX control panel to 'Maximum battery'. Then use setIGP command bundled with setPLL to lower 266MHz/320Mhz core render clocks. Sometimes the OC wall is the iGPU.

Usually when do such overclocks the RAM timings need to be slowed down too. Presumably your system is booting with the CAS=6. If you removed that entry using say Thaiphoon Burner, can you get the the system to boot with the slower CAS=7 entry? I'd like to say thank you for this magnificent work.

I've been using RW everything for some years now, mainly to write to my C2D's registers so I could disable IDA and change VIDs(voltages). I tried in the past to figure some way to make RWe write to the PLL registers via commands, but never got it working. Thank you for pointing me in the right direction.

I know that nowadays people ditched the old C2Ds and are now running on i7 and so forth, but for people like me that still have that old laptop at home and want to give it a new life, I would like to suggest some addictions to your script. For control and stability purposes, it would be wise to include an IDA disable routine plus VID modification for everyone that still use those models. What we need to do is to write directly to the MSR registers via the address 0x199. Bit 0 of EDX enables or disables IDA, a functionality that is useful performance wise but can lead to instability if used while OCing. Changing that bit to 1 disables IDA. Next is the VID control area which consists in the first two hex values of the EAX. It is useful if you want to fine tune your OC while keeping the temperatures in their lowest possible values, reducing the voltage until the desired frequency is no longer stable.

We can even create very low power usage profiles, with lower voltages and if desired lower frequencies(or SLFM) that can easily be toggled when OC is not needed(like doing some light work or just browsing the web). The syntax of the command is this.

In the meantime I've been playing around with RWe and the SMBus. It seems that in my system(ICS9LPR363) writing all at once can sometimes randomly crash the system instantly.

I've altered the routine in a way that only one byte is changed per run. That way I've stopped this to happening. My script(still in a basic state) consists in calling several bat files, each one with one run. In the first I change the voltages to max and disable the IDA, then run 3 bat files with one byte change each(only need to change 3 bytes). Main script bat. Hi, i was looking for something to overclock gpu intel gma 500.

I have noticed that you are using rweverthing to change freq with your setigp and gmaboost. From gma500 datasheet graphic clock controll is a little bit different from others intel gpu. Shri Krishna Bansuri Dhun Free Download.

GCFC is located in: Address F0h-F3h Default 00000002h Size 32bit Bit 31:2 are reserved 3:2 10b 01=ratio is 2:1 1:0 10b ->01=ratio is 2:1 for 200mhz at fsb 100mhz 266mhz at 133mhz 10=ratio is 3:2 for 200mhz at 133mhz Opening intel vga device with rweverithing F0=06 F1=00 F2=FF F3=01 (gma500 at 200mhz). What do you think? On my device fsb is 133mhz but with standard setting 3:2 gma is set to 200. I need to change to ratio 2:1 Maybe you can get more infos on gma500booster.blogspot. Hey guys, I'm kinda new to setPLL and I was trying it out on my different computers.

They were not the ones with the.lut files pre-made. So i just tried creating the mypll.lut file, and hoped to get to OverClock it from there. Just wondering if there was a something i was missing out, as when i create mypll.lut file, it says instructions are within the file, so I open up the file, and try to add BCLKs in the BCLK part, wasn't sure how it works, but figured id try that. I'm trying this out on a Lenovo x120e. SetPLL was written originally because I wanted to overclock a 2530P's FSB to run faster CPU+MEM and more importantly, overclock the pci-e bus for faster eGPU performance. It uses look up table files (.LUT) to program your PLL, an idea that I got from perusing a setFSB clone for Linux. I also wanted it to be *free* so other 2530P users could do the same.

It was important too that users could add their own PLL to be supported. Anybody who has a programmable (not TME-locked) PLL, has the PLL datasheet and can decipher it would be able to add support for their machine. SetPLL is also considerably faster at programming the PLL than setFSB is. To answer your question, it will depend on how programmable you PLL is to answer whether the FSB and pci-e clocks can be programmed separately. The example LUT files included with setPLL have both the FSB and PCI-E clocks for several PLLs where both can have both programmed. I found that pci-e overclocks over 12% usually result in the wifi card failing. Hi, thanks for this program!

I am trying to overclock my old Inspiron 9300 just for fun. I have found my PLL on the motherboard, it's ICS954201. Using SetFSB, the PCI slider is disabled for this PLL.

This results in the overclock quickly becoming unstable after only 1-2MHZ FSB increase. It looks like the HDD locks up. If I create my own LUT file, do you think I'll be able to increase FSB and specify the stock PCI-E clock?